| 摘要 |
A method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec is disclosed. In one embodiment, the GPIO_INT bit (i.e. bit 0 in slot 12 in the AC-link's SDATA_IN line) is utilized as an interrupt flag to indicate when data requested by the controller from the slow peripheral is returned and is available to be read by the controller. The GPIO_INT bit can also be used to indicate when a write into the slow peripheral is completed. In this embodiment, a "peripheral ready bit" or a "peripheral ready signal" originated from the slow peripheral is used to set the GPIO_INT bit. Another embodiment is directed to controllers which ignore the GPIO_INT bit as a source of interrupt. To accommodate these controllers, one of the GPIO bits is used to send the value of the "peripheral ready bit" to the controller. Upon receipt of the peripheral ready bit as one of the GPIO bits from the codec, the controller would interrupt the host CPU and the host CPU is made aware that the data requested from the slow peripheral is returned and is available to be read. The GPIO bit can also be used to indicate that a write into the slow peripheral has been completed. In yet another embodiment, the software running on the host CPU successively checks the peripheral ready bit, which is a designated bit in one of the codec's vendor reserved registers, to find out when the peripheral ready bit has been set. When the peripheral ready bit is set, and so detected by the software, the software would be alerted to the fact that the register from which data was requested now contains the requested data, and the requested data is then read by the software. The designated bit can also be used to indicate that a write into the slow peripheral has been completed.
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