| 摘要 |
Input/output AC characteristics of a hard macro cell is specified in advance, delay cells 15 and 16 are provided in the input and output sides of the hard macro cell, and signal propagation delay times of the delay cells 15 and 16 are set so as to satisfy the specifications. These delay times are determined in such a way that no timing error occurs at the data inputs D of the D flip-flops 11 and 22 on condition that D flip-flops 20 and 22 are arranged outside the hard macro cell 10A, the data output end Q of the D flip-flop 20 is directly connected by a line to the data input end DI of the hard macro cell 10A, the data input end of the external synchronous flip-flop 22 is directly connected to the data output end DO of the hard macro cell 10A, and a clock CLK is commonly provided to the clock input ends CK of the hard macro cell 10A and the D flip-flops 20 and 22.
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