发明名称 HIGH WITHSTAND VOLTAGE MOS TRANSISTOR AND MANUFACTURING METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide the manufacturing method of a high withstand voltage MOS transistor where the boundary of a low concentration diffusion area surrounding a drain area can be matched with a field oxidized film formed between a gate and a drain area in terms of self-matching, resulting in high withstand voltage and the less dispersion of a transistor characteristic. SOLUTION: The transistor has a p- well 13 formed on a p- type substrate 1, an n- well 14 formed adjacent to the p- well 13, the oxidized film 11c formed on the n- well detached from the boundary of the p- well 13 and the n- well 14 by a prescribed distance, a channel forming area 25 formed from a p- area 13b' and the p- well 13 by changing the n- well 14 from the oxidized film 11c to the p- well 13 to the p- area 13b', and a drain electrode part 21 being an n+ area formed in a low diffusion n- area 14b by making the n- well 14 to be the low diffusion n- area 14b.
申请公布号 JP2002222940(A) 申请公布日期 2002.08.09
申请号 JP20010019642 申请日期 2001.01.29
申请人 VICTOR CO OF JAPAN LTD 发明人 KAWAMOTO IPPEI
分类号 H01L29/78;(IPC1-7):H01L29/78 主分类号 H01L29/78
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