| 摘要 |
PROBLEM TO BE SOLVED: To avoid significant roll back in design work at the time of adding/ deleting logic elements. SOLUTION: A clock tree is formed in a logical space 21 and logic elements 35 sharing a branch point P0 are added to or deleted from a downstream block 34 comprising a plurality of logic elements connected to a branch point P0 specified in the clock tree. Skew is equalized between the downstream block 34 and other block 33 by altering the length of wiring B1 between the branch point P0 and a clock buffer 31 connected with the branch point P0 on the upstream. Skew can be substantially equalized between the downstream block 34 and other block 33 by altering the inner resistance of the clock buffer 31. Since the inner resistance is altered discontinuously, length of the wiring B1 is corrected eventually.
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