发明名称 MULTI-CORE DSP DEVICE HAVING COUPLED SUB-SYSTEM MEMORY BUS FOR GLOBAL DMA ACCESS
摘要 <p>PROBLEM TO BE SOLVED: To make different DMA controllers efficiently cooperate with each other in DMA data transfer between sub-systems. SOLUTION: The respective DMA controllers are constituted to be coupled to respective memory buses, so as to control the respective control busses. A memory bus multiplexer is connected between a subsystem memory bus and the each DMA controller, and is set to make all DMA controllers control the respective memory buses, using an arbiter. The each memory bus is also controlled by a host port interface via the memory bus multiplexer. An excellent access to the memory bus is provided for the respective DMA controllers and the host port interface, using a round-robin arbitration technique.</p>
申请公布号 JP2002222163(A) 申请公布日期 2002.08.09
申请号 JP20010349047 申请日期 2001.11.14
申请人 TEXAS INSTRUMENTS INC 发明人 REIMER JAY B;HOPKINS HARLAND GLENN;NGUYEN TAI H;LUO YI;MCGONAGLE KEVIN A;JONES JASON A;NGUYEN DUY Q;SMITH PATRICK J
分类号 G06F9/30;G06F13/16;G06F13/28;G06F13/362;G06F15/78;(IPC1-7):G06F13/362 主分类号 G06F9/30
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