| 摘要 |
A multi-channel clock recovery circuit is provided that generates pairs of recovered half-speed clocks. Each pair of half-speed clocks has a relative phase relationship of 180° and are capable of registering input data of a data channel at the eye of the input data. The multi-phase clock recovery circuit includes a voltage controlled oscillator outputting a plurality of half-speed reference clocks. Each of a plurality of clock recovery circuits include a phase locked loop having a phase multiplexor, the phase multiplexor receiving the plurality of half-speed reference clocks and selectively outputting four recovered half-speed clocks each having a half-speed frequency relative to the input data. The four recovered clocks are used as a feedback reference clocks in the phase locked loop and two of the four recovered half-speed clocks are used to synchronize input data.
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