发明名称 |
Electronic test circuit for memory component has command evaluation circuit controlling multiplexer to apply first or second address to address bus depending on command |
摘要 |
<p>The circuit has an address selection circuit (9) connected to first and second address memories (10,11) for storing first and second addresses, a multiplexer (15) connected to the address memories and to an address bus (3) and a command evaluation circuit (13) connected to the multiplexer and that controls it to apply the first or second address to the address bus depending on a command concerning the memory component. Independent claims are also included for the following: a method of generating data and testing a memory component.</p> |
申请公布号 |
DE10101999(A1) |
申请公布日期 |
2002.08.08 |
申请号 |
DE2001101999 |
申请日期 |
2001.01.18 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
LUEPKE, JENS;ERNST, WOLFGANG;KUHN, JUSTUS;MUELLER, JOCHEN;SCHITTENHELM, MICHAEL;POECHMUELLER, PETER;KRAUSE, GUNNAR |
分类号 |
G11C29/56;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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