发明名称 |
High voltage transistor using P+ buried layer |
摘要 |
A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
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申请公布号 |
US2002105054(A1) |
申请公布日期 |
2002.08.08 |
申请号 |
US20020091990 |
申请日期 |
2002.03.06 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
TSAI JUN-LIN;LIU RUEY-HSIN;HWANG JEI-FENG;LIU KUO-CHIO |
分类号 |
H01L21/331;H01L29/08;H01L29/732;(IPC1-7):H01L21/824;H01L21/822;H01L29/00;H01L27/082;H01L27/102;H01L29/70;H01L31/11 |
主分类号 |
H01L21/331 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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