CAPACITOR AND CAPACITOR CONTACT PROCESS FOR STACK CAPACITOR DRAMS

摘要

A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.