Damascene double-gate mosfet structure and its fabrication method

摘要

The present invention provides a method for fabricating sub-0.05 mum double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 mum double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.