发明名称 |
Intercalling between native and non-native instruction sets |
摘要 |
A data processing system 118 is provided that supports execution of both native instructions using a processor core and non-native instructions that are interpreted using either a hardware translator 122 or a software interpreter. Separate explicit return to non-native instructions and return to native instructions are provided for terminating subroutines whereby intercalling between native and non-native code may be achieved with reduced processing overhead. Veneer non-native subroutines may be used between native code and non-native main subroutines. The veneer non-native subroutines may be dynamically created within the stack memory region of the native mode system.
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申请公布号 |
US2002108103(A1) |
申请公布日期 |
2002.08.08 |
申请号 |
US20010887561 |
申请日期 |
2001.06.25 |
申请人 |
NEVILL EDWARD COLLES |
发明人 |
NEVILL EDWARD COLLES |
分类号 |
G06F9/40;G06F9/30;G06F9/318;G06F9/38;G06F9/45;G06F9/455;G06F9/48;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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