Phase locked loop apparatus

摘要

A phase locked loop apparatus 40 comprises an analogue phase locked loop 41 having a sampling phase detector 42 arranged to determine an error signal 44 corresponding to the phase difference between a reference frequency 43 and a frequency 50 generated by a voltage controlled oscillator 49. The error signal 44 is used in a feedback pathway 51 to control the frequency 50 generated by the voltage controlled oscillator 49 so as to reduce the error signal 44 over time. A second phase locked loop 53 comprises a digital phase locked loop unit 54 arranged to determine a direction indicator corresponding to the phase difference between the reference frequency 43 and the frequency 50 generated by the voltage controlled oscillator 49 and a microprocessor unit 55 that is arranged to vary the error signal 44 in a predetermined manner in accordance with the direction indicator until the value of the error signal 44 is within a predefined value range. <IMAGE>