| 摘要 |
<p>The Test Access Port (TAP) functions of a plurality of components arranged on a single chip (10) are managed by selectively driving the TAP function (20, 30, 40) of each of the components with respective clocks (TCK, DCK), whilst the further signals for driving the TAP function (TDI, TDO, TMS, NTRST) are used in shared mode among the various components. Preferably, associated to the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks (DCK, TCK) are generated on board the chip (10). <IMAGE></p> |
