| 摘要 |
PURPOSE:To inspect memory IC wherein a data pin and an address pin are made common even with respect to the operation bringing about the dynamic change-over of said pins, by interposing a multiplexer between an address generating part, a data generating part and a pin corresponding signal line. CONSTITUTION:When a timing generating part 16 generates a test cycle signal 18, an algorithmic address generating part 10 starts the generation of address data and an algorithmic data generating part 12 or a sequential data generating part 14 starts the generation of data information. At the same time, a multiplexer control part 24 reverses the state of a selection signal 26. For example, when it is assumed that the signal 26 becomes an '1' state, the address data is sent to a pin corresponding signal line 20 through a multiplexer 22. When the next signal 18 is generated, the signal 26 is reversed to a '0' state and the data information is sent out to the line 20. As mentioned above, inspection can be performed while the data information or address data is dynamically selected to be supplied to the common use pin at every cycle.
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