发明名称 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate
摘要 A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.
申请公布号 US6429109(B1) 申请公布日期 2002.08.06
申请号 US20010017953 申请日期 2001.12.14
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD 发明人 ZHENG JIA ZHEN;QUEK ELGIN;ZHOU MEI SHENG;YEN DANIEL;ANG CHEW HOE;LIM ENG HUA;CHA RANDALL
分类号 H01L21/28;H01L29/51;(IPC1-7):H01L21/476 主分类号 H01L21/28
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