发明名称 |
Reference signal switchover clock output controller |
摘要 |
A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.
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申请公布号 |
US6429707(B1) |
申请公布日期 |
2002.08.06 |
申请号 |
US20010911642 |
申请日期 |
2001.07.19 |
申请人 |
SEMTECH CORPORATION |
发明人 |
LAMB JONATHAN;BRUCHNER WOLFGANG;LANSDOWNE RICHARD |
分类号 |
H03D13/00;H03L7/083;H03L7/099;(IPC1-7):H03L7/06 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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