发明名称 Method for testing a memory device having two or more memory arrays
摘要 A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.
申请公布号 US6430094(B1) 申请公布日期 2002.08.06
申请号 US20000571206 申请日期 2000.05.16
申请人 MICRON TECHNOLOGY, INC. 发明人 WALLER WILLIAM K.
分类号 G11C29/00;G11C29/12;(IPC1-7):G11C7/00 主分类号 G11C29/00
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