发明名称 |
Configuration bus interface circuit for FPGAs |
摘要 |
A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.
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申请公布号 |
US6429682(B1) |
申请公布日期 |
2002.08.06 |
申请号 |
US20010865813 |
申请日期 |
2001.05.25 |
申请人 |
XILINX, INC. |
发明人 |
SCHULTZ DAVID P.;HUNG LAWRENCE C.;GOETTING F. ERICH |
分类号 |
H03M13/09;(IPC1-7):H03K19/173 |
主分类号 |
H03M13/09 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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