发明名称 Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)
摘要 A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1'), and a second data operand bit group corresponding to a second data operand (D2'). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.
申请公布号 US6430684(B1) 申请公布日期 2002.08.06
申请号 US19990431562 申请日期 1999.10.29
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 BOSSHART PATRICK W.
分类号 G06F9/305;G06F9/30;G06F9/315;(IPC1-7):G06F9/305;G06F9/308;G06F9/345;G06F7/06 主分类号 G06F9/305
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