| 摘要 |
A data processing system provided with a CPU for reading at units of 32 bits per read cycle, a font card that requires read accesses of either 16 or 8 bits per cycle by accessing a specific address area, and an address specifying control circuit positioned between the CPU and font card. When accessing the specific address area, the CPU provides information on the data width for access and the low-order portion of the address to the address specifying control circuit. Based on this data, the address specifying control circuit outputs the low-order portion of the address to the font card for accessing the font card at the prescribed unit of bits, regardless of the address data output from the CPU. For example, when performing a 16 bit read, the second to lowest order bit (ADR01) is set to 0 in the first read cycle, and the low-order 16 bits of data is considered valid. In the second read cycle, ADR01 is set to 1, and the high-order 16 bits of data is considered valid. The address accessed by the CPU is the same for both the first and second read cycles.
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