| 摘要 |
PURPOSE: A phase detector of a digital phase locked loop(PLL) is provided, which minimizes a quantization error generated while converting an analog phase difference into digital data, and improves a performance of the digital phase locked loop remarkably. CONSTITUTION: According to the phase detector(310) detecting a phase difference of a frequency in a digital phase locked loop(PLL), a count unit(311) counts numbers repetitively and continuously without reset according to a system clock. A latch unit(312) latches the first count value of the count unit according to an inputted reference clock, and outputs the first count value and the second count value latched at a previous reference clock. And an arithmetic calculation unit calculates a difference between the first count value and the second count value being output from the latch unit. The count unit comprises an N bit counter.
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