发明名称 ARITHMETIC UNIT AND PARALLEL ARITHMETIC UNIT
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic unit capable of optimizing a logical level, preventing an increase in constituting information, preventing the deterioration of area efficiency as an integrated circuit, improving operation efficiency, and reducing electric power consumption. SOLUTION: This arithmetic unit is provided with a first selecting device 11 for selecting factor inputs C0I to CkI according to a control signal ASEL, a second selecting device 12 for selecting data inputs D0I to DmI according to a control signal BSEL, a third selecting device 13 for selecting cascade inputs P0 to Pn-2 according to a control signal CSEL, an ALU 14 for executing a logical operation according to an instruction of a control signal ALUMD with output signals of the first to third selecting devices as input, a MAC 15 for executing an operation according an instruction of a control signal MACMD with the output signals of the first to third selecting device as input, and a fourth selecting device 16 for selecting either of an output signal of ALU 14 and an output signal of the MCA 15 according to a control signal ESEL.
申请公布号 JP2002215603(A) 申请公布日期 2002.08.02
申请号 JP20010012524 申请日期 2001.01.19
申请人 SONY CORP 发明人 OZAWA KUNIHIKO
分类号 G06F7/00;G06F17/10;G06F17/14 主分类号 G06F7/00
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