发明名称 TIMING CONSTRAINT GENERATING METHOD TO LOGICAL CIRCUIT, TIMING CONSTRAINT GENERATING PROGRAM TO LOGICAL CIRCUIT, AND PROGRAM RECORDING MEDIUM FOR GENERATING TIMING CONSTRAINT TO LOGICAL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To minimize the number of constraint set as units for subjects for delay inspection, and achieve further efficiency of delay inspection to each path. SOLUTION: A timing constraint matrix b comprising time constraint to each path between start point side/end point side flip-flops in a combinational circuit is formed, from which constraint set capable of simultaneously satisfying all of reaching timing and demanded timing of the start point side/end point side flip flops(FF) based on the time constraint are determined. Rows of the matrix b represent FF0-5 on the start point side, and columns represent FF6-12 on the end point side. There is no time constraint to a path between 0 and 6, and a time constraint between path 0 and 6 is 15. The constraint set of the row b is, for example, an set of the columns 6, 10, 11, and 12 (excluding 0 of the row of×), and a set of the columns 7, 8, and 9. Before determining the constraint set, contraction and split of the timing constraint matrix are conducted, and minimum covering problems for constraint set candidates are solved.
申请公布号 JP2002215711(A) 申请公布日期 2002.08.02
申请号 JP20010347206 申请日期 2001.11.13
申请人 FUJITSU LTD 发明人 MATSUNAGA TAEKO
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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