| 摘要 |
PROBLEM TO BE SOLVED: To provide a microprocessor capable of reducing useless machine cycles in a processor in an interruption operation mode. SOLUTION: This microprocessor is provided with a first storing means 1 for storing a first instruction code group, an address outputting means 5 for outputting first address information to the first instruction storing means, a second instruction storing means 2 for storing a second instruction code group to be processed in the interruption operation mode, an instruction decoding means 3 having a selection circuit capable of selecting either a first instruction code 101 from the first instruction storing means or a second instruction code 102 from the second storing means and also having a decoder for decoding the selected instruction, and a controlling means 4 for outputting second address information 107 for outputting the second instruction code to the second instruction storing means in the interruption operation mode and also for outputting a selection signal 106 for selecting the second instruction code for the selection circuit of the instruction decoding means.
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