| 摘要 |
PROBLEM TO BE SOLVED: To constitute a synchronizing separation circuit capable of stably outputting vertical synchronizing signals by using a digital circuit. SOLUTION: In an up counter 22, the position of the vertical synchronizing signal is counted from the front edge of a horizontal synchronizing signal H by a clock CLK. Whether the vertical synchronizing signal is an equal phase or a shift phase is discriminated on the basis of a count value in a circuit 24. Stable horizontal data which are the number of the clocks corresponding to one horizontal cycle are multiplied by 1 and 1.5 and the count value of the position of the vertical synchronizing signal is subtracted respectively in subtractors 34 and 35. In a down counter 25, the output of the subtractors 34 and 35 is selected on the basis of an equal/shift discriminated result and down counting is performed by the clock CLK with the selected output as an initial value. The position at which the count value by the down counter 25 is O is defined as the front edge of the vertical synchronizing signal V to be outputted. In a vertical synchronizing signal preparation circuit 27, the signal of a prescribed width is attained and the vertical synchronizing signal V is generated and outputted.
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