| 摘要 |
PROBLEM TO BE SOLVED: To properly process in an architecture pipe-lining of a CISC instruction which is hard to be made into pipe-line. SOLUTION: This variable length instruction set CPU is constituted of an instruction resister means IR:1 having a plurality of resisters IR00:12, IR01:13, IR02:14, and IR03:15 equivalent to the maximal instruction length connected so as to be serially transmitted, and stores an instruction obtained by an instruction fetching operation in the plurality of resisters IR00:12, IR01:13, IR02:14, and IR03:15 serially trasnsmittably connected to each other in the instruction resister means IR:1 starting from the head resister IR00:12. The instruction fetch operation is performed, so that it is done concurrently with an instruction shift operation by serially transmitting the instructions stored in the resister.
|
