发明名称 WIRING DELAY VIOLATION CORRECTING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a wiring delay violation correcting device which can correct wiring without permitting existing wiring to cause delay violation. SOLUTION: In the rewiring processing of a net which becomes delay violation in the correction of the wiring layer of an LSI layout pattern, a violation net input means 2 for inputting a violation net, an area dividing means 4 for dividing a designated correction area into a plurality of areas, a wiring area deciding means 5 for performing ranking with a wiring congestion degree as a reference and deciding a wiring route in order from a lowest rank, a shift margin calculating means 6 for calculating the shift margin of the respective nets from timing information of wiring, and a wiring means 7 for performing wiring by preferentially moving wiring or the net close to the net of the large shift margin in the respective areas, are disposed.
申请公布号 JP2002217301(A) 申请公布日期 2002.08.02
申请号 JP20010012840 申请日期 2001.01.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUI TORU;KOTANI ATSUSHI;SATO KOICHI
分类号 G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G06F17/50
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