发明名称 DEVICE AND METHOD FOR ESTIMATING BLOCK MATCHING MOTION WITH SMALL NUMBER OF CLOCK CYCLES
摘要 <p>PROBLEM TO BE SOLVED: To provide a method and device for estimating block matching motion with a small number of clock cycles which are used for a very large scale integrated circuit, etc. SOLUTION: This motion estimating device includes a prescribed number of first processing means (810 and 830) for receiving a search area data signal at the leading edge of a clock and calculating the absolute value of the difference between the search area data signal and a reference block data signal, and a prescribed number of second processing means (820 and 840) for receiving the search area data signal at the trailing edge of the clock and calculating the absolute value of the difference between the search area data signal and the reference block data signal. The first processing means (810 and 830) are alternately connected to the second processing means (820 and 840).</p>
申请公布号 JP2002218476(A) 申请公布日期 2002.08.02
申请号 JP20010066546 申请日期 2001.03.09
申请人 KOREA TELECOMMUN 发明人 YOON JONG-SEONG
分类号 H04N19/423;H03M7/36;H04N5/14;H04N7/24;H04N19/50;H04N19/513;H04N19/57;(IPC1-7):H04N7/32 主分类号 H04N19/423
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