| 摘要 |
<p>A buffer circuit comprising a first power terminal (Vcc), a second power terminal (Vss), a complementary first FET pair (P1, N1) arranged between the first and second power terminals (Vcc, Vss) to receive an external signal, a complementary second FET pair (P2, N2) which is arranged between the first and second power terminals (Vcc, Vss) and whose input terminal is connected to an output terminal of the first FET (P1,N1) pair, and voltage drop means (D1, D2) arranged between the first power terminal (Vcc) and the first FET pair (P1, N1).</p> |
