Electronic circuit device and its design method

摘要

A method for designing an electronic logic circuit device for reducing delay time degradation due to crosstalk between a wire in question and a wire adjacent thereto and for preventing the increase of designing work in case signal arrival time of each of the wire in question and the adjacent wire is dynamically changed according to the input pattern. Delay time degradations is calculated from range of relative signal arrival time (relative window) of the wire in question and the adjacent wire, and when there is violation of design constraint, delay time degradation is reduced by preventing the relative window from touching a curve of delay time degradation.