| 摘要 |
PURPOSE: A frequency synthesizer using a high frequency phase locked loop and a method for controlling a total delay time of the frequency synthesizer are provided, which performs a normal dividing operation even though the maximum allowable delay time is decreased because a modulus of a prescaler is reduced. CONSTITUTION: A prescaler(40) has a modulus(V), and divides a high frequency input signal inputted from the external into V or V+1 in response to a modulus control signal. An N-counter(44) outputs divided signals by dividing the prescaler dividing signal with the first dividing ratio and the second dividing ratio in turn, and generates the first control signal in case of the first dividing ratio, and generates the second control signal in case of the second dividing ratio. A prescaler control part(42) generates a control signal having the first logic level in response to the first control signal being output from the N-counter and the second logic level in response to the second control signal. And a delay control part(46) controls a delay time of the control signal being output from the prescaler control part, and outputs the above control signal as the modulus control signal, in response to the delay control signal inputted from the external.
|
