| 摘要 |
A circuit and method for generating a pulse width modulated signal (510) is disclosed. The circuit includes a clock that generates a clock signal having a plurality of clock pulses, the clock pulses being spaced by weighted intervals during a signal period and a register (1612) that receives a data word (1230) with a plurality of data bits, and that generates a pulse width modulated signal by comparing each data bit to a corresponding one of the clock pulses. In an alternate embodiment, a programmable pulse width modulation generator circuit (1220a-b) and method fro generating a pulse width modulated signal with a variable duty cycle is disclosed. The generator circuit includes a data loading circuit (1615) or receiving a data word representing the desired duty cycle of the pulse width modulated signal to be generated.
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