Method and apparatus for verification of a circuit layout

摘要

A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.