发明名称 |
Floating wordline using a dynamic row decoder and bitline VDD precharge |
摘要 |
A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.
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申请公布号 |
US6426914(B1) |
申请公布日期 |
2002.07.30 |
申请号 |
US20010839105 |
申请日期 |
2001.04.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DENNARD ROBERT H.;HSU LOUIS L.;KIRIHATA TOSHIAKI K. |
分类号 |
G11C7/22;G11C8/08;G11C8/10;G11C11/4076;G11C11/408;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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