发明名称 |
Duty-cycle correction circuit |
摘要 |
A duty-cycle correction circuit corrects a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency. The device acts to translate a non-50% duty-cycle clock to an accurate 50% duty-cycle clock by utilizing a divide-by-2 frequency divider and a multiply-by-2 clock doubler to achieve conversion. The duty-cycle correction circuit increases the translation back to its original frequency while using an analog negative feedback to maintain an accurate 50% duty cycle.
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申请公布号 |
US6426660(B1) |
申请公布日期 |
2002.07.30 |
申请号 |
US20010943665 |
申请日期 |
2001.08.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HO SHIU C.;BLUM DAVID W. |
分类号 |
H03K5/00;H03K5/156;(IPC1-7):H03K3/017;H03B19/00;H03K21/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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