| 摘要 |
PROBLEM TO BE SOLVED: To reduce processing load of a microcomputer in a digital modulator implementing modulating processing, e.g. MSK modulation, through processing of the microcomputer. SOLUTION: Assuming a case where 1200 Hz and 1800 Hz are assigned, respectively, to logical value '1' and '2' and transmission data of 1200 b/s is subjected to MSK modulation. A data converting section 14 converts transmission data '1' into a bit sequence '000111' or '111000' and transmission data '0' into a bit sequence '110011' or '001100', and sets conversion results in a shift register 16. The shift register 16 shifts the data thus set according to a clock of 7200 Hz from a shift register drive clock generating section 18 and outputs the shifted data in serial. That output is smoothed through a low-pass filter 20, thus obtaining a desired MSK modulation signal.
|
