DATA BIT-TO-CLOCK ALIGNMENT CIRCUIT WITH FIRST BIT CAPTURE CAPABILITY
摘要
A plurality of data signal delay (102) and sampling (103) circuits are connected to a clock terminal and a parallel data terminal to provide time-slice bit samples of each information bit of a parallel data signal. A comparator (104) and decision (105) circuit compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal. A multiplexer circuit (107) outputs the selected time-slice bit sample of each word bit of the parallel data signal as the phase-aligned parallel data signal. A first-bit intialization circuit (106) causes the time-slice bit samples corresponding in time to the logic state transition of the data ready signal to be output as a first one or more information bits of the phase-aligned data signal.
申请公布号
WO02057891(A1)
申请公布日期
2002.07.25
申请号
WO2002US01612
申请日期
2002.01.22
申请人
MAYO MEDICAL FOUNDATION FOR MEDICAL EDUCATION AND
发明人
ZABINSKI, PATRICK, JOSEPH;DEGERSTROM, MICHAEL, JOHN;GILBERT, BARRY, K.