DATA PROCESSING APPARATUS INCLUDING A PLURALITY OF PIPELINE PROCESSING MECHANISMS IN WHICH MEMORY ACCESS INSTRUCTIONS ARE CARRIED OUT IN A MEMORY ACCESS PIPELINE

摘要

Abstract of Disclosure The memory access arithmetic operation instruction is executed in the data processing apparatus including a memory access pipeline and arithmetic operation pipeline. The decoding and development of the memory access arithmetic operation are carried out after the memory access arithmetic operation instruction is input to the memory access pipeline and the memory access results and the memory access arithmetic instruction are output to the arithmetic operation pipeline.