| 摘要 |
One embodiment of the present invention provides a system that converts transport packets into Internet Protocol (IP) packets using circuitry that is driven by an incoming clock signal from the transport stream. The system operates by receiving a stream of transport packets along with an associated incoming clock signal at an interface module. Next, the system assembles an IP packet from a plurality of transport packets using circuitry that is driven by the incoming clock signal. Next, the IP packet is stored into a memory. Finally, the system sends the IP packet across a network to a destination IP address using circuitry that is driven by an interface module clock signal. This interface module clock signal is generated locally within the system containing the interface module. In one embodiment of the present invention, the system assembles a plurality of IP packets into a High-level Data Link Control (HDLC) frame. This reduces the number of interrupts caused in downstream systems because only a single interrupt is required to process a HDLC frame, even if it contains multiple IP packets, instead of an interrupt for each IP packet. Furthermore, the system periodically sends the HDLC frame with any IP packets are available to be sent, instead of waiting for a minimum number of IP packets. In one embodiment of the present invention, the system inserts wait states of programmable duration between HDLC frames in order to allow a downstream receiver sufficient time to process successive HDLC frames. |
