Cache-Speicher und Verfahren zur Adressierung

摘要

The invention relates to a cache memory whose addresses are divided into a tag, index and offset. Means are provided as hardware for carrying out a reversible univocal transformation between the respective tag part of the address and an encoded tag address. The index field of the address of the cache memory can also be encoded by means of another reversibly univocal mapping which maps the index field onto an encoded index field. A corresponding hardware unit is also provided therefor.