| 摘要 |
An improved computer processor architecture in the form of an apparatus with a mirrored stack and method of using the same are provided that enable increased functionality for a plurality of processor events. The architecture removes from software the burden of preserving and maintaining the processor registers upon certain processor events, thereby improving coding efficiency and the utilization of processor time. Finally, the architecture provides a mechanism for speeding up CALL and RETURN instruction execution times and for other instances where processor register must be preserved to prevent loss or corruption.
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