VARIABLE-FREQUENCY PULSE GENERATOR

摘要

The output ( theta 2) of a digital adder (13) before held by a first data holding circuit (14) is compared with a first reference value (D1) by a first data comparator (15) and compared with a second reference value (D2) by a second data comparator (16). Thereby one cycle of pulse train fout output control is changed from four periods (T1 to T4) of a reference clock to two periods (T1, T2). The output ( theta 1) of the first data holding circuit (14) is compared with the first reference value (D1) by a third data comparator (19). Thereby the latch timing of an overflow signal is changed from T4 of a reference clock fb to T1.