PLL circuit having a variable output frequency

摘要

A phase locked loop (PLL) circuit includes a VCO (11) having a parallel resonant circuit including a first capacitance (C4) implemented by a reverse-biased diode and a second capacitance (C1 to C3) implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance (C4). If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance (C1 to C3) is corrected for compensating the deviation. <IMAGE>