| 摘要 |
PURPOSE: A phase locked loop(PLL) circuit and locking control method therefor is provided to generate an output having an accurate frequency together with reducing a locking time independent of manufacturing process and temperature effects. CONSTITUTION: A PLL circuit includes a phase frequency detector(31) for detecting a phase difference by comparing a phase of feedback signal with that of a reference signal, an electron pump(32) for pumping electrons in response to the output signals from the phase frequency detector(31), a loop filter(15) for filtering the output signals from the electron pump(32), a voltage control oscillator(VCO)(34) for varying the frequency of the feedback signals in response to the output signals from the loop filter(15), a register(35) for storing the digital signals, a digital-to-analog(DA) converter(36), a lock detector(37) for determining by receiving the output signals from the phase frequency detector(31) whether or not the feedback signals are locked with the reference signals and an analog-to-digital(AD) converter(38). The DA converter(36) controls the voltage level of the output signals from the loop filter(15) by converting the digital signals stored in the register(35). The AD converter(38) supplies the digital signals by converting the output signals from the loop filter(15) into the digital signals, which is activated when the lock detector(37) outputs a signal representing a status of locking.
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