发明名称 Semiconductor integrated circuit device and manufacture method therefor
摘要 <p>The object of the present invention is to prevent elements in a triple-well MOS transistor from being destroyed due to an increase in current consumption or a thermal runaway of a parasitic bipolar transistor. &lt;??&gt;In a triple-well NMOS transistor 311 comprising a P well area 22 formed within an N well area 28 and a MOSFET formed in the P well area 22, an impurity-diffused area 29 having a lower impurity concentration than an N&lt;+&gt; drain area 25 is formed close to the N&lt;+&gt; drain area 25, thereby restraining substrate current. The impurity concentration of the P well area 22 is increased to reduce the current gain of a parasitic bipolar transistor. To further reduce the current gain, a punch-through stopper area may be formed. The impurity concentration of the impurity-diffused area 29 is set to equal that of an N- LDD area 31 of a fine CMOS device integrated on the same substrate 1. These areas are formed during a single ion injection step. &lt;IMAGE&gt;</p>
申请公布号 EP1225627(A2) 申请公布日期 2002.07.24
申请号 EP20020250303 申请日期 2002.01.16
申请人 FUJI ELECTRIC CO., LTD. 发明人 KITAMURA, AKIO
分类号 H01L21/8238;H01L27/092;(IPC1-7):H01L21/823 主分类号 H01L21/8238
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