| 摘要 |
The present invention provides a logic unit and integrated circuit for clearing interrupts. The logic unit is coupled to a bus operating in a first clock domain, and is arranged to interface between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. In accordance with the present invention, the logic unit comprises an interrupt source, responsive to a signal issued by the device, to assert a first interrupt signal in the second clock domain, and output logic, responsive to the first interrupt signal-to output a second interrupt signal via the bus to a processor operating in the first clock domain. The processor is arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt. The logic unit also includes clear generation logic arranged, whilst the first interrupt signal is asserted, to be responsive to receipt of the clear request signal to assert a clear signal to the interrupt source and to assert a control signal to the output logic. The output logic is responsive to receipt of the control signal to stop outputting the second interrupt signal, whilst the interrupt source is responsive to the clear signal to de-assert the first interrupt signal, the de-assertion of the first interrupt signal causing a clear acknowledge signal to be generated. The clear generation logic is then responsive to the clear acknowledge signal to de-assert the clear signal. This approach enables an interrupt generated in the second clock domain to be efficiently cleared without impacting the efficiency of the processor operating in the first clock domain.
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