发明名称 |
Semiconductor memory module having double-sided stacked memory chip layout |
摘要 |
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
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申请公布号 |
US6424030(B2) |
申请公布日期 |
2002.07.23 |
申请号 |
US20010863450 |
申请日期 |
2001.05.24 |
申请人 |
HITACHI, LTD.;HITACHI TOBU SEMICONDUCTOR, LTD.;AKITA ELECTRONICS CO., LTD. |
发明人 |
MASAYUKI WATANABE;TOSHIO SUGANO;SEIICHIRO TSUKUI;TAKASHI ONO;YOSHIAKI WAKASHIMA |
分类号 |
G11C5/00;H01L23/495;H01L25/065;H01L25/10;H05K1/14;H05K3/34;H05K3/36;(IPC1-7):H01L23/02 |
主分类号 |
G11C5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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