| 摘要 |
Each memory cell is connected to a paired bit line. Each of the bit lines is connected to a PMOS transistor as a transfer gate, and each of the bit lines is connected to a first local sense amplifier via the PMOS transistor. These first local sense amplifiers are connected to a second local sense amplifier. The second local sense amplifier is connected to a data bus for outputting data stored in these cells. Since the semiconductor has multistage local sense amplifier, sense time for high-speed data outputting can be improved while increasing power at the sensing is restrained.
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