发明名称 |
System and method for reading data from a programmable logic device |
摘要 |
A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.
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申请公布号 |
US6425077(B1) |
申请公布日期 |
2002.07.23 |
申请号 |
US19990312024 |
申请日期 |
1999.05.14 |
申请人 |
XILINX, INC. |
发明人 |
LE THACH-KINH;ALLAMSETTY CHAKRAVARTHY K.;CARMICHAEL CARL H.;MANDHANIA ARUN K.;ST. PIERRE, JR. DONALD H.;THERON CONRAD A. |
分类号 |
G01R31/3185;G01R31/319;G06F3/00;(IPC1-7):G06F3/00 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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