发明名称 Controlling burst sequence in synchronous memories
摘要 A system and apparatus for controlling a burst sequence in a synchronous memory is described. In one embodiment, the system comprises a synchronous memory and a burst read device coupled to the synchronous memory. In one embodiment, the burst read device is configured to sense a page of data as a current page from the synchronous memory, wherein the current page contains a fixed number of words of data. The device is further configured to latch the current page of data, and synchronously read the current page of data, one word at a time. In an alternate embodiment, the burst read device further comprises a wrap-bit. If the wrap-bit is not set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a sequential burst read order. If the wrap-bit is set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a non-sequential burst read order.
申请公布号 US6425062(B1) 申请公布日期 2002.07.23
申请号 US19990395870 申请日期 1999.09.14
申请人 INTEL CORPORATION 发明人 KENDALL TERRY L.;MCKEE KENNETH G.;RAO KISHORE
分类号 G11C16/02;G06F12/00;G06F12/02;G11C7/10;G11C16/06;G11C16/08;G11C16/26;(IPC1-7):G06F12/00 主分类号 G11C16/02
代理机构 代理人
主权项
地址